Production method for anneal wafer and anneal wafer

ABSTRACT

The present invention is a method of producing an annealed wafer wherein a silicon single crystal wafer having a diameter of 200 mm or more produced by the Czochralski (CZ) method is subjected to a high temperature heat treatment in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100-1350° C. for 10-600 minutes, and before the high temperature heat treatmen, a pre-annealing is performed at a temperature less than the temperature of the high temperature heat treatment, so that the growth of slip dislocations is suppressed by growing oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein the generation and growth of slip dislocations generated in a high temperature heat treatment are suppressed and the defect density in the wafer surface layer is lowered even in the case of a silicon single crystal wafer having a large diameter of 200 mm or more, and the annealed wafer.

TECHNICAL FIELD

[0001] The present invention relates to a method of producing anannealed wafer and an annealed wafer, particularly relates to a methodof producing an annealed wafer and an annealed wafer wherein thegeneration of slip dislocations is lowered and the deflect density on awafer surface layer is lowered even in the case of a wafer having alarge diameter.

BACKGROUND ART

[0002] Recently, high integration and fineness have been promoted in adevice process, and the integrity of a device active region in a surfacelayer and the improvement of gettering ability to capture impuritiessuch as metals caused by increase of bulk micro defects (BMD) formed byoxide precipitates (oxygen precipitation nuclei) in a bulk have beenrequired of a silicon wafer.

[0003] In response to these requirements, various approaches have beenattempted. For example, in order to eliminate defects (mainly grown-indefects) on a wafer surface, it has been performed that a wafer obtainedby the Czochralski method (CZ method) is subjected to a high temperatureheat treatment in an atmosphere of an argon gas or a hydrogen gas, or amixture gas atmosphere thereof at 1100-1350° C. for 10-600 minutes.

[0004] However, in the case that a silicon wafer having a large diameterof 200 mm or 300 mm or more is subjected to the high temperature heattreatment as described above, slip dislocations, which penetrate a waferfrom its back side to the front, are remarkably generated. Such slipdislocations are grown further in a device process, they cause a failurein a device process, and they have been one of factors of lowering ayield.

[0005] Moreover, in the case that a silicon wafer having a largediameter of 300 mm or more is subjected to the high temperature heattreatment, as compared to the case that a silicon wafer having adiameter of 200 mm is subjected to the high temperature heat treatment,the generation of slip dislocations is remarkably increased, these slipdislocations have penetrated a annealed wafer from its back side to thefront, and have been detected by a visual inspection or a particlecounter. Namely, in the above heat treatment process, it was impossibleto eliminate crystal defects in a wafer surface and suppress slipdislocations at the same time.

DISCLOSURE OF THE INVENTION

[0006] The present invention was accomplished in view of the problemsmentioned above, and the object of the present invention is to provide amethod of producing an annealed wafer wherein the generation and growthof slip dislocations generated in a high temperature heat treatment aresuppressed and the defect density in the wafer surface layer is loweredeven in the case of a silicon single crystal wafer having a largediameter of 200 mm or more, and to provide the annealed wafer.

[0007] In order to accomplish the above object, the present inventionprovides a method of producing an annealed wafer wherein a siliconsingle crystal wafer having a diameter of 200 mm or more produced by theCzochralski (CZ) method is subjected to a high temperature heattreatment in an atmosphere of an argon gas, a hydrogen gas, or a mixturegas thereof at a temperature of 1100-1350° C. for 10-600 minutes, andbefore the high temperature heat treatment, a pre-annealing is performedat a temperature less than the temperature of the high temperature heattreatment to suppress growth of slip dislocations by growing oxideprecipitates.

[0008] As described above, the growth of slip dislocations can besuppressed by increase of each size of oxide precipitates. Therefore,before the silicon single crystal wafer is subjected to the hightemperature heat treatment, a pre-annealing is performed at atemperature less than the temperature of the high temperature heattreatment, and thereby, each size of oxide precipitates in the wafer canbe grown largely. And then, by performing the high temperature heattreatment, the growth of slip dislocations during the high temperatureheat treatment can be suppressed and crystal defects can be eliminated.

[0009] In this case, it is preferable that the pre-annealing isperformed at least in a single stage for 2 hours or more.

[0010] As described above, the pre-annealing is performed at least in asingle stage for 2 hours or more, and thereby, the growth of slipdislocations can be suppressed by surely growing oxide precipitates andthe effect of lowering crystal defects in a wafer surface can be furtherenhanced.

[0011] In this case, it is preferable that a temperature range of thepre-annealing is 950-1050° C .

[0012] As described above, since a temperature range of thepre-annealing is 950 or more, oxide precipitates can be grownefficiently without taking along time, and since the temperature rangeis 1050° C. or less, oxide precipitates can be grown without growingslip dislocations in the pre-annealing. Moreover, since thepre-annealing is performed within such a temperature range, crystaldefects in a wafer surface can be effectively lowered by the hightemperature heat treatment.

[0013] And, in this case, it is preferable that the pre-annealing isperformed in two stages of a first annealing (at a temperature T1) and asecond annealing (at a temperature T2) having T1<T2.

[0014] As described above, when the pre-annealing is performed in twostages and the relation of each heat treatment temperature is T1<T2,each size of oxide precipitates can be grown to a certain degree by thefirst annealing, then the second annealing is performed at a temperatureT2 higher than T1, and thereby, the growth of slip dislocations can besurely suppressed, and at the same time, oxide precipitates can be grownfurther in a relatively short period of time.

[0015] Moreover, in this case, it is preferable that the temperature T1of the first annealing is 1000° C. and the temperature T2 of the secondannealing is 1050° C.

[0016] As described above, if the temperature T1 of the first annealingis 1000° C., each size of oxide precipitates can be increased withoutgrowing slip dislocations, and since each size of oxide precipitates isgrown to a certain degree by the first annealing of 1000° C., even inperforming the second annealing of 1050° C., the growth of slipdislocations can be surely suppressed and oxide precipitates can begrown further in a relatively short period of time.

[0017] And, it is preferable that in the pre-annealing, when the siliconsingle crystal wafer is loaded into a heat treatment furnace, atemperature of the heat treatment furnace is controlled to be 700° C. orless, a wafer loading rate is controlled to be 50 mm/min or less, and arecovery temperature-rising rate is controlled to be 5° C./min or less.

[0018] Since a silicon single crystal wafer is loaded into a heattreatment furnace under the above described conditions, the generationof scratches on a wafer back side when loading a wafer, which is one offactors of the generation of slip dislocations, can be lowered, andthereby slip dislocations caused by starting from the scratches can bereduced.

[0019] And, it is preferable that a silicon single crystal wafer dopedwith nitrogen and having a nitrogen concentration of 1×10¹³-5×10¹⁵/cm³and an oxygen concentration of 10-25 ppma (JEIDA) is used as the siliconsingle crystal wafer.

[0020] As described above, when the nitrogen concentration of the waferis 1×10¹³/cm³ or more, the density of oxide precipitates (1×10⁹/cm³ ormore) to effectively suppress slip dislocations can be easily obtained,and when the nitrogen concentration is 5×10¹⁵/cm³ or less, a formationof a single crystal is not hindered when a CZ single crystal is pulled.And, when the oxygen concentration of the wafer is 10-25 ppma (JEIDA:Japan Electronic Industry Development Association Standard), asufficient density of oxide precipitates can be obtained by the effectof nitrogen doping without generating slip dislocations originating fromoxide precipitates.

[0021] Moreover, it is preferable that a silicon single crystal waferwhich is produced under the condition that the generation of voiddefects is suppressed when a silicon single crystal is produced by theCZ method is used as the silicon single crystal wafer to be subjected tothe high temperature heat treatment.

[0022] As described above, if a wafer which is produced under thecondition that the generation of void defects is suppressed when asilicon single crystal is produced by the CZ method is used as thesilicon single crystal wafer, in addition to the effect that the growthof slip dislocations can be suppressed during a high temperature heattreatment, since the wafer essentially having extremely few void defectsis subjected to the high temperature heat treatment and oxideprecipitates near its surface are almost annihilated by out-diffusion inthe high temperature heat treatment, an extremely high quality DZ layercan be obtained.

[0023] In this case, it is preferable that an OSF density of the siliconsingle crystal wafer produced under the condition that the generation ofvoid defects is suppressed is 1000 numbers/cm² or less.

[0024] As described above, if the silicon single crystal wafer is awafer in which the OSF density observed after performing the thermaloxidation treatment is 1000 numbers/cm² or less, OSF nuclei existingnear a wafer surface can be surely annihilated by the high temperatureheat treatment.

[0025] And according to the present invention, there can be provided anannealed wafer having a large diameter wherein the growth of slipdislocations can be suppressed even if the wafer is subjected to thehigh temperature heat treatment and the defect density near a wafersurface is lowered.

[0026] As explained above, according to the present invention, when thehigh temperature heat treatment of 1100° C. or more is performed, thepre-annealing is performed at the temperature less than that of the hightemperature heat treatment, and thereby, even in the case that a siliconsingle crystal wafer has a large diameter of 200 mm or more, an annealedwafer wherein the defect density in the wafer surface is small and slipdislocations are lowered can be provided.

BRIEF EXPLANATION OF THE DRAWINGS

[0027]FIG. 1 is a diagram showing the existence of slip dislocations oneach annealed wafer surface when each heat treatment time of the firstannealing (1000° C.) and the second annealing (1050° C.) is changed.

[0028]FIG. 2 is a diagram showing the existence of slip dislocations oneach annealed wafer surface when each heat treatment time of the firstannealing (800° C.) and the second annealing (1000° C.) is changed.

[0029]FIG. 3 is a diagram showing comparisons of measured crystal defectdensities of each surface of annealed wafers under differentpre-annealing conditions.

BEST MODE FOR CARRYING OUT THE INVENTION

[0030] Hereinafter, embodiments of the present invention will beexplained. However, the present invention is not limited thereto.

[0031] Conventionally, in a high temperature annealing performed byusing an argon gas, a hydrogen gas or the like at a high temperature(1100-1350° C.) for a long time, in order not to contain slipdislocations in a wafer, after a wafer is loaded into a heat treatmentfurnace at a low temperature, the temperature is gradually increased toa designated heat treatment temperature. In this high temperature heattreatment, the reason why the heat treatment temperature is 1100° C. ormore is to effectively eliminate defects near a wafer surface, and thereason why the heat treatment temperature is 1350° C. or less is toprevent problems such as deformation of the wafer, metal contamination,etc. However, such a conventional method has a problem that in the casethat a wafer having a diameter of 200 mm or 300 mm or more is subjectedto the heat treatment, when its temperature is a high temperature ofover 1050° C., slip dislocations, which penetrate a wafer from its backside to the front, are remarkably generated.

[0032] One of the causes is that when a silicon wafer is loaded into aheat treatment furnace, a temperature distribution in a surface of thesilicon wafer is enlarged. And thereby, the wafer itself is deformed, sothat a part of a contact portion of the wafer with a boat is broken, andscratches are generated on the wafer back side. After that, bysubjecting the silicon wafer to a high temperature heat treatment, slipdislocations are grown starting from the scratches on the wafer backside and they penetrate the wafer to its front side.

[0033] Accordingly, inventors of the present invention has conceivedthat in order to lower crystal defects in a wafer surface and tosuppress the generation and the growth of slip dislocations, if thegeneration of scratches on a wafer back side can be reduced when a waferis loaded into a furnace and if, before performing a heat treatment at atemperature of 1100° C. or higher, oxide precipitates, which have theeffect of suppressing the growth of slip dislocations, can be grown to acertain size or more under the condition that slip dislocations are notgenerated nor grown, crystal defects in a wafer surface can beeliminated and slip dislocations of an annealed wafer can be lowered.And they accomplished the present invention by assiduous studies andinvestigations.

[0034] Namely, before a mirror-polished wafer, which is sliced from asingle crystal ingot grown by the CZ method and polished, is subjectedto a high temperature heat treat in an atmosphere of an argon gas, ahydrogen gas, or a mixture gas thereof at a temperature of 1100-1350° C.for 10-600 minutes, the wafer is firstly subjected to a pre-annealing ata temperature less than the temperature of the high temperature heattreatment under the condition that slip dislocations are not generatedto grow oxide precipitates in the wafer. After that, by performing thehigh temperature heat treatment, a wafer such that crystal defects onand near the wafer surface are eliminated and a gettering layer byoxygen precipitation exists inside the wafer can be produced withoutgrowing slip dislocations.

[0035] Particularly, when the pre-annealing is performed at least in asingle stage for 2 hours or more, and then the high temperature heattreatment is performed, the generation of slip dislocations can besurely suppressed and the effect of lowering crystal defects can befurther enhanced.

[0036] Additionally, it is possible that the pre-annealing and the hightemperature heat treatment (defect eliminating annealing) of 1100° C. orhigher is continuously performed without unloading a wafer from afurnace, or it is possible that after the pre-annealing, the temperatureis once lowered and a wafer is unloaded from a furnace, and then thewafer is loaded into the heat treatment furnace again and a defecteliminating annealing is performed. In consideration of productivity, itis preferable to continuously perform the processes.

[0037] In this case, if the temperature of the pre-annealing is lessthan 950° C., it takes a long time to grow oxide precipitates, which isnot efficiently. And if the temperature of the pre-annealing is over1050° C., slip dislocations are remarkably generated. And therefore, itis preferable that the temperature range of the pre-annealing is950-1050° C.

[0038] Moreover, it is preferable that the pre-annealing is performed intwo stages. First, each size of oxide precipitates existing in a waferis grown to a certain degree in the first annealing (at a temperatureT1) , and then the second annealing is performed at a temperature T2higher than T1, and thereby, the growth of slip dislocations in thesecond annealing can be surely suppressed, and at the same time, oxideprecipitates can be grown further in a short period of time, so that thegrowth of slip dislocations in a subsequent high temperature heattreatment of 1100° C. or more can be sufficiently suppressed, andcrystal defects of an annealed wafer can be further lowered after thehigh temperature heat treatment.

[0039] In this case, there is the possibility that if the heat treatmenttemperature is 1000° C., although slip dislocations are not grown, itmay take a long time to grow oxide precipitates, and if the heattreatment temperature is 1050° C., oxide precipitates and slipdislocations may be grown at the same time. Accordingly, when the heattreatment temperature of the first annealing is set at 1000° C. and theheat treatment temperature of the second annealing is set at 1050° C.,oxide precipitates can be grown without growing slip dislocations in thefirst annealing to the size that slip dislocations is not grown in thesecond annealing, after that, by growing oxide precipitates further inthe second annealing, oxide precipitates can be grown in a short periodof time, and crystal defects can be eliminated without growing slipdislocations even in the high temperature heat treatment of 1100° C. ormore. Therefore, when the temperature T1 of the first annealing is 1000°C. and the temperature T2 of the second annealing is 1050° C. asdescribed above, slip dislocations can be efficiently suppressed, oxideprecipitates can be grown in a short period of time, and the defectdensity of the annealed wafer can be lowered.

[0040] And, slip dislocations, which penetrate a wafer to its frontside, are caused by two factors of generation of scratches on a waferback side when loading a wafer into a furnace and the growth by asubsequent heat treatment, as aforementioned. Conditions of scratchesgenerated on a wafer back side vary by changing wafer loadingconditions. Also, if many scratches are generated on a wafer back sidewhen loading a wafer into a furnace, slip dislocations are grownstarting from the scratches. Accordingly, when a wafer is loaded into aheat treatment furnace in the pre-annealing, a temperature of the heattreatment furnace is controlled to be 700° C. or less, a wafer loadingrate is controlled to be 50 mm/min or less, and a recoverytemperature-rising rate is controlled to be 5° C./min or less, andthereby, the generation of scratches on a wafer back side can be loweredwhen loading a wafer, and the growth of slip dislocations can beprevented thereafter. Particularly, if the wafer loading temperature isover 700° C., the larger the diameter of a wafer is, the larger thetemperature distribution in a wafer becomes when loading a wafer, sothat the wafer is greatly deformed. As a result, the friction betweenthe wafer and a boat is increased and sources of generation of slipdislocations are increased. Therefore, it is preferable that the waferloading temperature is 700° C. or less.

[0041] Additionally, the term a recovery temperature-rising rate usedherein is the temperature-rising rate to recover the furnace temperaturefrom the lowered value to the prescribed value in the case that when awafer is loaded into a heat treatment furnace of which temperature isset at a prescribed temperature, the temperature in the furnace islowered less than the prescribed temperature.

[0042] Moreover, it is preferable that the wafer used in the presentinvention is a silicon single crystal wafer doped with nitrogen. If thewafer is a silicon single crystal wafer doped with nitrogen and having anitrogen concentration of 1×10¹³/cm³ or more, the density of oxideprecipitates (1×10⁹/cm³ or more), which is effective in suppressing slipdislocations, can be easily obtained. However, if a nitrogenconcentration is over 5×10¹⁵/cm³, there is a possibility that formationof a single crystal is prevented when pulling a CZ single crystal, whichcauses decrease of productivity. Therefore, it is preferable that thenitrogen concentration of the wafer is 1×10¹³-5×10¹⁵/cm³

[0043] Also, in this case, if the oxygen concentration of the wafer is10 ppma (JEIDA) or more, a sufficient density of oxygen precipitates canbe obtained by the effect of nitrogen doping. However, on the contrary,if the oxygen concentration exceeds 25 ppma, oxide precipitation is toomuch, and slip dislocations caused by the precipitates are easy to benewly generated. Accordingly, it is preferable that the oxygenconcentration of the wafer is 10-25 ppma (JEIDA).

[0044] Furthermore, in the present invention, it is preferable that asilicon single crystal wafer produced under the condition that thegeneration of void defects is suppressed when a silicon single crystalis produced by the CZ method is used as the silicon single crystal waferto be subjected to the high temperature heat treatment. At this point,as for the condition that the generation of void defects is suppressed,as described in the Japanese patent Laid-open applications Nos.11-147786, 11-157996, etc., for example, there can be provided acondition that a silicon single crystal is pulled in a N-region (neutralregion) in which the generation of defects such as void defects whichare agglomeration of vacancy type point defects and dislocations causedby excessive interstitial silicons is suppressed by controlling a V/Gvalue which is a ratio of a pulling rate V and a temperature gradient Gnear a solid-liquid interface in a pulling crystal when a silicon singlecrystal is pulled by the CZ method. Specifically, the V/G is controlledby adjusting a furnace structure (hot zone structure) in a pullingapparatus and a pulling rate, and thereby, the growth of the siliconsingle crystal can be performed under the condition to be a N-region, sothat the crystal having no void defects serving as the agglomeration ofvacancy type point defects can be obtained.

[0045] By subjecting the silicon single crystal wafer produced undersuch a condition to the high temperature heat treatment of the presentinvention, in addition to the effect that the growth of slipdislocations in the high temperature heat treatment can be suppressed,the wafer inherently having extremely few void defects is subjected tothe high temperature heat treatment and oxygen precipitates near thesurface are almost annihilated by out-diffusion in the high temperatureheat treatment, so that an annealed wafer having an extremely highquality DZ layer can be obtained.

[0046] In this case, it is preferable that the silicon single crystalwafer produced under the condition that the generation of void defectsis suppressed is a wafer in which the OSF density detected on itssurface by performing a high temperature oxidation heat treatment is1000 numbers/cm² or less. OSF nuclei causing the generation of OSF by ahigh temperature thermal oxidation are Grown-in oxide precipitateshaving a comparatively large size, and if such OSF nuclei exist near awafer surface in high density, OSF nuclei may not be annihilatedsufficiently by out-diffusion even in the high temperature heattreatment of the present invention and remain therein. However, if theOSF density of a silicon single crystal wafer is 1000 numbers/cm² orless, OSF nuclei existing near a wafer surface can be surely annihilatedby the out-diffusion in the high temperature heat treatment.

[0047] Hereinafter, the present invention will be further explained indetail.

[0048] First, an ingot containing nitrogen of 5×10¹³/cm³ (calculatedvalue) and oxygen of 15 ppma (JEIDA), and having a diameter of 300 mmwere grown by the MCZ method, and then wafers were prepared by slicingthem from the ingot.

[0049] After that, in order that prepared wafers were subjected to aheat treatment, the wafers were loaded into a heat treatment furnace.Wafer loading conditions at that time were set as follows. Thetemperature of the heat treatment furnace was 700° C., the wafer loadingrate was 100 mm/min, and the recovery temperature-rising rate was 10°C./min.

[0050] After the wafers were loaded into the furnace, a pre-annealingwas performed in an atmosphere of Ar at 1000° C. for 0-16 hours+at 1050°C. for 0-12 hours, and then, a high temperature heat treatment waspreformed at 1200° C. for 1 hour. After the annealing, the existence ofslip dislocations existing on each surface of the annealed wafersobtained from each heat treatment condition was inspected. These resultsare shown in FIG. 1. Each plot and straight lines connecting them inFIG. 1 are a borderline which indicates whether slip dislocations aregenerated or not by the high temperature heat treatment (at 1200° C. for1 hour), and it means that slip dislocations are generated below theborderline and slip dislocations are not generated on or above theborderline (additionally, in the case that the pre-annealing was notperformed but only the high temperature heat treatment was performed at1200° C. for 1 hour, slip dislocations were frequently generated).

[0051] Also, defect densities of each surface of the annealed wafersobtained under the heat treatment condition of at 1000° C. for 2hours+at 1050° C. for 5 hours+at 1200° C. for 1 hour, and the heattreatment condition of at 1000° C. for 4 hours+at 1050° C. for 4hours+at 1200° C. for 1 hour (each condition is that slip dislocationsare not generated) were measured and these results are shown in FIG. 3.

[0052] As shown in FIG. 1, by properly setting the temperature and timeof the pre-annealing before the high temperature heat treatment of 1200°C., annealed wafers having no slip dislocation on the surface thereofcan be obtained, and among them, the wafers annealed under the heattreatment condition of at 1000° C. for 2 hours+at 1050° C. for 5hours+at 1200° C. for 1 hour and the heat treatment condition of at1000° C. for 4 hours+at 1050° C. for 4 hours+at 1200° C. for 1 hour,became the annealed wafers having no slip dislocation which wereobtained by the comparatively short-time pre-annealing. Also, theannealed wafers produced by these two conditions have extremely fewsurface defects as shown in FIG. 3.

[0053] Next, by means of the MCZ method, wafers were prepared under thesame conditions as in the above, and they were loaded into the heattreatment furnace under the same wafer loading conditions as in theabove. After that, a pre-annealing was performed in an atmosphere of Arat 800° C. for 2-16 hours+at 1000° C. for 7-18 hours, and then a hightemperature heat treatment was performed at 1200° C. for 1 hour. Afterthe annealings, the existence of slip dislocations existing on eachsurface of the annealed wafers obtained under each heat treatmentcondition was inspected. These results are shown in FIG. 2 (The way oflooking at FIG. 2 is the same as FIG. 1). Also, defect densities of eachsurface of annealed wafers obtained under the heat treatment conditionof at 800° C. for 4 hours+at 1000° C. for 12 hours+at 1200° C. for 1hour, and the heat treatment condition of at 800° C. for 8 hours+at1000° C. for 9 hours+at 1200° C. for 1 hour were measured and theseresults are shown in FIG. 3.

[0054] As shown in FIG. 2, by properly setting the temperature and timeof the pre-annealing, the annealed wafers having no slip dislocation onthe surface thereof can be obtained, and among them, the wafer annealedunder the heat treatment condition of at 800° C. for 4 hours+at 1050° C.for 12 hours+at 1200° C. for 1 hour can be the annealed wafer having noslip dislocation which was obtained by the comparatively short-timeannealing.

[0055] From the results of FIGS. 1 and 2, it is found that in the caseof considering the heat treatment time, when the oxygen precipitationtreatment is performed by a pre-annealing having the combination of1000° C.+1050° C., the annealed wafer having no slip dislocation can beefficiently obtained in a shorter time compared to a pre-annealinghaving the combination of 800° C.+1000° C.

[0056] Also, as shown in FIG. 3, in the above pre-annealing having thecombination of 1000° C.+1050° C. or 800° C.+1000° C., as compared todefect densities on each surface layer of annealed wafers obtained underthe heat treatment conditions of a comparatively short time among heattreatment conditions which can eliminate slip dislocations on each wafersurface, the defect density of the annealed wafer subjected to the heattreatment having the combination of 800° C.+1000° C.+1200° C. is about5-10 times higher than that of the annealed wafer subjected to the heattreatment having the combination of 1000° C.+1050° C.+1200° C.Therefore, it was found that elimination of crystal defects in the hightemperature heat treatment was suppressed in the wafer subjected to theheat treatment having the combination of 800° C.+1000° C.+1200° C.

[0057] Although the reason is not clear, when the heat treatment of thecombination of 800° C.+1000° C.+1200° C. is performed, it is consideredthat in the pre-annealing of 800° C.+1000° C., defects which aredifficult to be eliminated by the argon annealing of 1200° C. are grown.

[0058] From these results, it is also found that the density of crystaldefects in a surface layer of the wafer can be much lowered byperforming the pre-annealing having the combination of 1000° C.+1050°C., which is more effective.

[0059] Next, heat treatments were performed with different wafer loadingconditions in the pre-annealing.

[0060] First, an ingot containing nitrogen of 5×10¹³ atoms/cm³(calculated value) and oxygen of 15 ppma (JEIDA), and having a diameterof 300 mm was grown by the MCZ method, and then, wafers were prepared byslicing them from the ingot.

[0061] After that, in order that prepared wafers were subjected to aheat treatment, the wafers were loaded into a heat treatment furnace.The wafer loading conditions into the heat treatment furnace at thattime are shown in Table 1 as follows. TABLE 1 Temperature Wafer of HeatRecovery Loading Treatment Temperature- Condition Furnace Wafer LoadingRate rising Rate Condition 700° C. 100 mm/min 10° C./min 1 Condition700° C. 100 mm/min  5° C./min 2 Condition 700° C.  50 mm/min 10° C./min3 Condition 700° C.  50 mm/min  5° C./min 4

[0062] After wafers were loaded into the heat treatment furnace undereach wafer loading conditions, a pre-annealing was performed at 1000° C.for 2-8 hours+at 1050° C. for 2-8 hours, and then a high temperatureheat treatment was performed at 1200° C. for 1 hour.

[0063] As a result, when the wafer loading conditions were conditions1-3, by performing the annealing under the heat treatment condition ofat 1000° C. for 4 hours+at 1050° C. for 4 hours+at 1200° C. for 1 houras in the results of FIG. 1, crystal defects could be lowered and slipdislocations that penetrate the annealed wafer to the front side werenot generated. On the other hand, only when wafers were loaded into theheat treatment furnace under the condition 4, even by the annealingunder the heat treatment condition of at 1000° C. for 2 hours+at 1050°C. for 2 hours+at 1200° C. for 1 hour, i.e., the short timepre-annealing which shows results that slip dislocations were generatedin FIG. 1, the annealed wafer with low defect density having no slipdislocation which penetrate the wafer to its front side could beobtained.

[0064] From the above results, when the wafer loading condition is acondition in which the temperature of the heat treatment furnace is 700°C., the wafer loading rate is 50 mm/min, and the recoverytemperature-rising rate is 5° C./min, or a condition such that less loadis applied to the wafer than the above condition (700° C. or less, 50mm/min or less, and 5° C./min or less, respectively), growth of slipdislocations can be effectively suppressed.

[0065] Also, for confirmation, wafers were loaded into a heat treatmentfurnace under the conditions 1-4, and then annealed wafers which weresubjected to the high temperature heat treatment at 1200° C. for 1 hourwithout performing a pre-annealing and annealed wafers which weresubjected to the pre-annealing at 1000° C. for 2 hours and thensubjected to the high temperature heat treatment at 1200° C. for 1 hourwere prepared, after that, they were compared by measuring density ofcrystal defects and slip dislocations generated. As a result, as for theannealed wafer without a pre-annealing, slip dislocations possible to beobserved even by a visual inspection were remarkably generated in anycase without depending on the wafer loading conditions. However, as forthe annealed wafers subjected to the pre-annealing, the defect densityand slip dislocations generated were lowered not more than half of thatof the annealed wafer without a pre-annealing.

[0066] Namely, according to the present invention, by performing apre-annealing at the temperature less than the temperature of the hightemperature heat treatment before the high temperature heat treatment,the density of crystal defects of the annealed wafer can be surelylowered, and at the same time, the generation of slip dislocations canbe suppressed. In particular, as in the case that the pre-annealing isperformed in two stages, the annealed wafer having no slip dislocationat all can also be produced.

[0067] The present invention will be explained more specifically asdescribed in the examples and comparative examples below, but thepresent invention is not limited thereto.

EXAMPLE 1

[0068] First, raw material polycrystalline silicon was charged into aquartz crucible, a silicon wafer with a nitride film was chargedthereinto beforehand, and a silicon single crystal having a diameter of300 mm, P-type, orientation <100>, and doped with nitrogen was grown bythe MCZ method (content of nitrogen was 5×10¹³ atoms/cm³ (calculatedvalue) and content of oxygen was 15 ppma (JEIDA)). After that, thesingle crystal was sliced into a wafer, and the wafer was subjected tolapping, chamfering and polishing to be a mirror-polished wafer.

[0069] Next, in order to anneal the mirror-polished wafer obtained, thewafer was loaded into a heat treatment furnace. At that time, as for theloading condition of the wafer, the temperature of the heat treatmentfurnace was set at 700° C., the wafer loading rate was set at 50 mm/min,and the recovery temperature-rising rate was set at 5° C./min.

[0070] After the wafer was loaded into the heat treatment furnace, in anatmosphere of 100% Ar, a first annealing was performed at 1000° C. for 2hours, then a second annealing was performed at 1050° C. for 2 hours,followed by performing a high temperature heat treatment at 1200° C. for1 hour.

[0071] After the high temperature heat treatment, a surface of theannealed wafer was observed by X-ray topography and a surface inspectionapparatus (SP-1, made by KLA-Tencor Corporation.), and as a result, slipdislocation were not almost detected. And the defect density of thesurface of the annealed wafer obtained was measured by a defectevaluation apparatus (MO-601, made by Mitsui Mining and Smelting Co.,Ltd.), and as a result, a very low value of 1.5 numbers/cm² was shown.

[0072] Also, by using a wafer of the same specifications as the abovewafer, densities of oxide precipitates and sizes of oxide precipitateswere measured by an OPP (Optical Precipitate Profiler) made by HighYield Technology, which is infrared interferometric defect evaluationapparatus, in each case of before and after the first annealing, andafter the second annealing.

[0073] As a result, since each size of oxide precipitates before thefirst annealing was small, they could not be observed by the OPP. Foryour information, the lower limit of the size of oxygen precipitatespossible to be inspected by the OPP is about 50 nm. On the other hand,after the first annealing, the oxide precipitates were grown to a sizepossible to be inspected, which were 1.2 (a.u.) on the average.Moreover, it was found that after the second annealing, they were grownto 2.8 (a.u.) on the average. And the densities of oxide precipitates ofboth of after the first annealing and after the second annealing were4×10⁹ numbers/cm³.

[0074] Namely, it is presumed that since the size of oxide precipitatesare grown by the first and second annealings and the oxide precipitateswere formed at the sufficient density as described above, the generationof slip dislocations caused by the subsequent high temperature heattreatment was suppressed.

[0075] In addition, since the above OPP can not measure an absolutevalue of the defect size detected, the estimation was performed by arelative value using a.u. (arbitrary unit).

EXAMPLES 2-8 AND COMPARATIVE EXAMPLES 1 AND 2

[0076] First, raw material polycrystalline silicon was charged into aquartz crucible, a silicon wafer with a nitride film was chargedthereinto beforehand, and a silicon single crystal ingot having adiameter of 200 mm, crystal orientation <100>, P-type, and doped withnitrogen of 10 Ω·cm was grown by the CZ method (content of nitrogen was5×10¹³ atoms/cm³ (calculated value) and content of oxygen was 15 ppma(JEIDA)). After that, the silicon single crystal ingot was sliced intowafers, and the wafers were subjected to lapping, chamfering andpolishing to prepare mirror-polished wafers. The defect density of eachsurface of these mirror-polished wafers was measured by MO-601 (made byMitsui Mining and Smelting Co., Ltd.), and as a result, the defectdensity was 55.3 numbers/cm².

[0077] The mirror-polished wafers manufactured as described above werecontinuously subjected to the heat treatments in an atmosphere of 100%Ar under each heat treatment condition described in Table 2 as followsby using a vertical type heat treatment furnace. In addition, at thattime, each condition of loading and unloading wafers was as follows.That is, the temperature of the heat treatment furnace was set at 700°C., the boat speed (wafer loading rate) was set at 50 mm/min, therecovery temperature-rising rate was set at 5° C./min, and after loadingthe wafers into the heat treatment furnace, the temperature of the heattreatment furnace was increased at the temperature-rising rate of 5°C./min. After the high temperature heat treatment, the defect density ofeach surface of the annealed wafers manufactured was measured by usingMO-601 (made by Mitsui Mining and Smelting Co., Ltd.) and the generationcondition of slip dislocations was observed by an X-ray topograph image.And, a 5-stage relative evaluation was performed in a way that the waferin which slip dislocations were not almost generated was ranked as 1 andthe wafer in which slip dislocations were generated the most was rankedas 5. These measured results are shown together in Table 2 as follows.TABLE 2 High Temperature Heat Generation Pre-Annealing TreatmentCondition Temper- Temper- Defect Of Slip ature Hour ature Hour DensityDislocation (° C.) (hr) (° C.) (hr) (numbers/cm²) (Rank) Example 2  9504 1200 1 1.1 1 Example 3 1000 4 1200 1 1.0 2 Example 4 1050 4 1200 1 1.23 Example 5 1000 2 1200 1 1.3 3 Example 6 1000 4 1200 1 1.0 2 Example 71000 8 1200 1 0.8 2 Example 8 1000 16  1200 1 0.5 1 Comparative None1200 1 2.6 5 Example 1 Comparative None 1200 4 1.3 5 Example 2

[0078] As shown in Table 2 described above, by subjecting to apre-annealing in a single stage for 2 hours or more before the hightemperature heat treatment, in particular, by subjecting to apre-annealing within the temperature range of 950-1050° C. (Examples2-4), the generation of slip dislocations could be suppressed and thedensity of crystal defects other than slip dislocations could also besurely lowered. Further, when the pre-annealing time was longer(Examples 5-8), the generation of slip dislocations could be furthersuppressed, and the effect of eliminating crystal defects could also befurther enhanced. However, in the case that the pre-annealing was notperformed before the high temperature heat treatment (ComparativeExamples 1 and 2), slip dislocations were remarkably generated on eachsurface of the annealed wafers, i.e., the generation of slipdislocations could not be suppressed. Also, it was found that as to theannealed wafers subjected to the pre-annealing according to the presentinvention, not only slip dislocations could be reduced, but also theeffect of eliminating crystal defects could be increased as compared tothe conventional case that only a high temperature heat treatment isperformed.

[0079] Moreover, it was confirmed that even if the experiment isrepeatedly performed under the same conditions as above, the sameresults as the Table 2 can be obtained, i.e., it is reproducible.

EXAMPLE 9

[0080] First, raw material polycrystalline silicon was charged into aquartz crucible, and a silicon single crystal having a diameter of 200mm, P-type and orientation <100> was grown under the condition that across section perpendicular to a growing direction of the crystalbecomes a N-region for an entire plane by controlling a V/G valueaccording to the MCZ method (nitrogen was not doped and content ofoxygen was 15 ppma (JEIDA)). After that, the single crystal was slicedinto wafers, and the wafers were subjected to lapping, chamfering andpolishing to be mirror-polished wafers.

[0081] In order to measure the OSF density of the surface of the wafer,one wafer was sampled. And, the wafer was subjected to a heat treatmentat 1000° C. for 3 hours+at 1150° C. for 100 minutes in an oxidizingatmosphere, then its surface was subjected to preferential etching toobserve its OSF density. As a result, it was confirmed that about 150numbers/cm² of the OSF was observed and the OSF density of themirror-polished wafer manufactured was 1000 numbers/cm² or less.

[0082] Next, the mirror-polished wafer manufactured was subjected to theheat treatment in an atmosphere of 100% Ar under the heat treatmentconditions described in Example 2 of Table 2 by using a vertical typeheat treatment furnace. At that moment, loading conditions of the waferwere as follows. That is, the temperature of the heat treatment furnacewas set at 700° C., the wafer loading rate was set at 50 mm/min, therecovery temperature-rising rate was set at 5° C./min. And after thewafer was-loaded into the heat treatment furnace, the temperature of theheat treatment furnace was increased at the temperature-rising rate of5° C./min.

[0083] After the high temperature heat treatment, the surface of theannealed wafer was measured by X-ray topography and a surface inspectionapparatus (SP-1, made by KLA-Tencor Corporation), and as a result, slipdislocation were not. almost confirmed (which is an equal level to therank 1 in Table 2).

[0084] Also, the defect density of the surface of the annealed waferobtained was measured by a defect evaluation apparatus (MO-601, made byMitsui Mining and Smelting Co., Ltd.), and as a result, a very low valueof 0.05 numbers/cm² was shown.

[0085] Moreover, using the wafers having the same specifications as theabove wafer, each density of oxide precipitates and sizes of oxideprecipitates were measured by the OPP in each case of before thepre-annealing and after the high temperature heat treatment.

[0086] As a result, since the size of oxide precipitates before thepre-annealing was small, they could not be observed by the OPP. On theother hand, oxide precipitates after the high temperature heat treatmentwere grown to a size possible to be inspected by the OPP, which were 2.5(a.u.) on the average. And the density of oxide precipitates was 5×10⁹numbers/cm³.

[0087] The present invention is not limited to the embodiment describedabove. The above-described embodiment is a mere example, and thosehaving substantially the same structure as that described in theappended claims and providing the similar functions and advantages areincluded in the scope of the present invention.

[0088] For example, in the above Examples, the case that the atmospherefor the high temperature heat treatment is argon is taken as an example,but the case that the high temperature heat treatment is performed in anatmosphere of hydrogen or a mixture atmosphere of hydrogen and argon canalso be applied the present invention to in the same way. And if atemperature of a high temperature heat treatment and a heat treatmenttime is within the range of the present invention, the present inventioncan be applied thereto in the same way.

1-10. (cancelled)
 11. A method of producing an annealed wafer wherein asilicon single crystal wafer having a diameter of 200 mm or moreproduced by the Czochralski (CZ) method is subject to a high temperatureheat treatment in an atmosphere of an argon gas, a hydrogen gas, or amixture gas thereof at 1100-1350° C. for 10-600 minutes, and before thehigh temperature heat treatment, a pre-annealing is performed at atemperature less than the temperature of the high temperature heattreatment to suppress growth of slip dislocations by growing oxideprecipitates.
 12. The method of producing an annealed wafer according toclaim 11, wherein the pre-annealing is performed at least in a singlestage for 2 hours or more.
 13. The method of producing an annealed waferaccording to claim 11, wherein a temperature range of the pre-annealingis 950-1050° C.
 14. The method of producing an annealed wafer accordingto claim 12, wherein a temperature range of the pre-annealing is950-1050° C.
 15. The method of producing an annealed wafer according toclaim 12, wherein the pre-annealing is performed in two stages of afirst annealing (at a temperature T1) and a second annealing (at atemperature T2) having T1<T2.
 16. The method of producing an annealedwafer according to claim 12, wherein the pre-annealing is performed intwo stages of a first annealing (at a temperature T1) and a secondannealing (at a temperature T2) having T1<T2.
 17. The method ofproducing an annealed wafer according to claim 12, wherein thepre-annealing is performed in two stages of a first annealing (at atemperature T1) and a second annealing (at a temperature T2) havingT1<T2.
 18. The method of producing an annealed wafer according to claim14, wherein the pre-annealing is performed in two stages of a firstannealing (at a temperature T1) and a second annealing (at a temperatureT2) having T1<T2.
 19. The method of producing an annealed waferaccording to claim 15, wherein the temperature T1 of the first annealingis 1000° C. and the temperature T2 of the second annealing is 1050° C.20. The method of producing an annealed wafer according to claim 16,wherein the temperature T1 of the first annealing is 1000° C. and thetemperature T2 of the second annealing is 1050° C.
 21. The method ofproducing an annealed wafer according to claim 17, wherein thetemperature T1 of the first annealing is 1000° C. and the temperature T2of the second annealing is 1050° C.
 22. The method of producing anannealed wafer according to claim 18, wherein the temperature T1 of thefirst annealing is 1000° C. and the temperature T2 of the secondannealing is 1050° C.
 23. The method of producing an annealed waferaccording to claim 18, wherein in the pre-annealing, when the siliconsingle crystal wafer is loaded into a heat treatment furnace, atemperature of the heat treatment furnace is controlled to be 700° C. orless, a wafer loading rate is controlled to be 50 mm/min or less, and arecovery temperature-rising rate is controlled to be 5° C./min or less.24. The method of producing an annealed wafer according to claim 11,wherein a silicon single crystal wafer doped with nitrogen and having anitrogen concentration of 1×10¹³-5×10¹⁵/cm³ and oxygen concentration of10-25 ppma (JEIDA) is used as the silicon single crystal wafer.
 25. Themethod of producing an annealed wafer according to claim 13, wherein asilicon single crystal wafer doped with nitrogen and having a nitrogenconcentration of 1×10¹³-5×10¹⁵/cm³ and oxygen concentration of 10-25ppma (JEIDA) is used as the silicon single crystal wafer.
 26. The methodof producing an annealed wafer according to claim 15, wherein a siliconsingle crystal wafer doped with nitrogen and having a nitrogenconcentration of 1×10¹³-5×10¹⁵/cm³ and oxygen concentration of 10-25ppma (JEIDA) is used as the silicon single crystal wafer.
 27. The methodof producing an annealed wafer according to claim 17, wherein a siliconsingle crystal wafer doped with nitrogen and having a nitrogenconcentration of 1×10¹³-5×10¹⁵/cm³ and oxygen concentration of 10-25ppma (JEIDA) is used as the silicon single crystal wafer.
 28. The methodof producing an annealed wafer according to claim 11, wherein a siliconsingle crystal wafer which is produced under a condition that generationof void defects is suppressed when a silicon single crystal is producedby the CZ method is used as the silicon single crystal wafer to besubjected to the high temperature heat treatment.
 29. The method ofproducing an annealed wafer according to claim 13, wherein a siliconsingle crystal wafer which is produced under a condition that generationof void defects is suppressed when a silicon single crystal is producedby the CZ method is used as the silicon single crystal wafer to besubjected to the high temperature heat treatment.
 30. The method ofproducing an annealed wafer according to claim 15, wherein a siliconsingle crystal wafer which is produced under a condition that generationof void defects is suppressed when a silicon single crystal is producedby the CZ method is used as the silicon single crystal wafer to besubjected to the high temperature heat treatment.
 31. The method ofproducing an annealed wafer according to claim 17, wherein a siliconsingle crystal wafer which is produced under a condition that generationof void defects is suppressed when a silicon single crystal is producedby the CZ method is used as the silicon single crystal wafer to besubjected to the high temperature heat treatment.
 32. The method ofproducing an annealed wafer according to claim 28, wherein an OSFdensity of the silicon single crystal wafer produced under the conditionthat generation of void defects is suppressed 1000 numbers/cm² or less.33. The method of producing an annealed wafer according to claim 29,wherein an OSF density of the silicon single crystal wafer producedunder the condition that generation of void defects is suppressed is1000 numbers/cm² or less.
 34. An annealed wafer produced by the methodof producing an annealed wafer according to claim
 11. 35. An annealedwafer produced by the method of producing an annealed wafer according toclaim
 13. 36. An annealed wafer produced by the method of producing anannealed wafer according to claim
 15. 37. An annealed wafer produced bythe method of producing an annealed wafer according to claim
 23. 38. Anannealed wafer produced by the method of producing an annealed waferaccording to claim
 24. 39. An annealed wafer produced by the method ofproducing an annealed wafer according to claim
 28. 40. An annealed waferproduced by the method of producing an annealed wafer according to claim32.